1. Field of the Invention
The invention relates in general to a mask and method of manufacturing a poly-silicon layer using the same, and more particularly to a mask and method of manufacturing a poly-silicon layer using the same applicable to the sequential lateral solidification technology.
2. Description of the Related Art
Along with the rapid advance in technology, planar display has been widely applied in portable electronic products such as notebook computer, personal digital assistant (PDA) and mobile phone. The Low-Temperature Poly-Silicon (LTPS) display panel uses a laser annealing method to transform an amorphous silicon (a-Si) layer into a poly-silicon layer, largely increasing the electron mobility of the thin film transistor (TFT). The design of the LTPS display panel, which integrates a panel driving circuit and an integrated circuit (IC) without using additional circuit boards, improves the flexibility in designing the panel and the circuit, and further brings greater potentials to the LTPS display panel. At present, the poly-silicon crystallization technology includes continuous grain silicon (CGS) technology, sequential lateral solidification (SLS) technology, CW-laser lateral crystallization (CLC) technology, selectively enlarging laser X'tallization (SELAX) technology, and so forth. The invention is exemplified by the sequential lateral solidification technology.
The sequential lateral solidification technology uses a mask equipped with a transparent region and an opaque portion to define a region of amorphous silicon layer on a substrate to be projected by the laser light. A part of the amorphous silicon layer corresponding to the transparent region is melted by the laser light and becomes a melted amorphous silicon layer, while the remaining part of the amorphous silicon layer corresponding to the opaque portion is not melted by the laser light. The temperature on the melted amorphous silicon is higher than the temperature on the remaining part of the amorphous silicon layer. The temperature gradient between the melted amorphous silicon and the remaining part of the amorphous silicon layer enables the melted amorphous silicon to crystallize lateral solidification and form a poly-silicon layer from the remaining part of the amorphous silicon layer towards the center of the melted amorphous silicon. Then, a substrate or a mask is moved so that the transparent region on the mask corresponds to a partial region on the remaining part of the poly-silicon layer, and that the above crystallization step is continued to perform the sequential lateral solidification. However, during the process of using the sequential lateral solidification technology to manufacture a poly-silicon layer, the sub-grain boundary is formed on the poly-silicon layer to reduce the inner strain generated by heat stress. Since the amount of sub-grain boundary is inversely proportional to electronic mobility, the occurrence of such boundary needs to be reduced so that the electronic mobility of the poly-silicon layer is improved.
Currently, there are a number of structural designs using mask area to reduce the amount of sub-grain boundary. For example, the structure of the mask applicable to the SLS technology and disclosed in United State Patent Application Publication No 2003/0088848 A1 is illustrated in FIG. 1. A mask 10 includes a mask body 11, and a first region 12, a second region 13, a third region 14 and a fourth region 15 formed in the mask body 11. The first region 12 has a number of first slits 12a and a number of first opaque portions 12b. The first slits 12a are parallel to and alternate with the first opaque portions 12b. The second region 13 has a number of second slits 13a and a number of second opaque portions 13b. The second slits 13a, which are parallel to and alternate with the second opaque portions 13b, are perpendicular to the first slits 12a. The third region 14 is positioned between the first region 12 and the second region 13, and has a number of third slits 14a and a number of third opaque portions 14b. The third slits 14a are parallel to and alternate with the third opaque portions 14b. The third slits 14a are parallel to the first slits 12a and correspond to the first opaque portions 12b. The width of the third slits 14a and that of the first slits 12a are respectively slightly larger than the width of the first opaque portions 12b and that of the third opaque portion 14b. The fourth region 15 is positioned between the second region 13 and the third region 14, and has a number of fourth slits 15a and a number of opaque portions 15b. The fourth slits 15a are parallel to and alternate with the fourth opaque portions 15b. The fourth slits 15a are parallel to the second slits 13a. The width of the second slits 13a and that of the fourth opaque portions 15a are respectively slightly larger than the width of the fourth opaque portions 15b and that of the second opaque portions 13b. 
As shown in FIG. 2, the mask 10 respectively moves along several directions 17a˜17d over every row on the amorphous silicon layer 16, so that every row on the amorphous silicon 16 is projected by the laser to crystallize a poly-silicon layer. Firstly, the mask 10 moves along the direction 17a when the first region 12 and the second region 13 are respectively the head and the tail. The laser light is projected onto the first row and that the sequential lateral solidification is performed to form poly-silicon. Next, the mask 10 moves along the direction 17b when the first region 12 and the second region 13 are respectively the tail and the head. The laser light is projected onto the second row, and that the sequential lateral solidification is performed to form poly-silicon. Then, the mask 10 is moved along the direction 17c, so that the laser light is projected onto the third row, and that the sequential lateral solidification is performed to form poly-silicon. Then, the mask 10 moves along the direction 17d, so that the laser light is projected onto the third row, and that the sequential lateral solidification is performed to form poly-silicon. Similarly, the mask 10 moves along an S-path to scan an amorphous silicon layer 16, so that every row on the amorphous silicon layer 16 is projected by the laser light to form poly-silicon crystallization. When the mask 10 moves along an S-path to scan the amorphous silicon layer 16, the extending direction of the first slits 12a and that of the third slits 14a are parallel to the directions 17a˜17d, while the extending direction of the second slits 13a and that of the fourth slits 15a are perpendicular to the directions 17a˜17d. 
When the mask 10 scans the odd-numbered rows of the amorphous silicon layer 16, the laser projecting regions corresponding to the third slits 14a alternate and partially overlap with the crystallization regions corresponding to the first slits 12a. The laser projecting regions corresponding to the second slits 13a alternate and partially overlap with the crystallization regions corresponding to the fourth slits 15a. Therefore, the fourth region 15 and the second region 13 are used to eliminate the sub-grain boundaries caused by the first region 12 and the third region 14. The third region 14 is used to melt and crystallize the corresponding non-crystallization region corresponding to the first region 12. The second region 13 is used to melt and crystallize the corresponding non-crystallization region corresponding to the fourth region 15.
Similarly, when the mask 10 scans the even-numbered row of the amorphous silicon layer 16, the laser projecting regions corresponding to the first slits 12a alternate and partially overlap with the corresponding crystallization regions of the third slits 14a. The laser projecting regions corresponding to the fourth slits 15a alternate and partially overlap with the crystallization regions corresponding to the second slits 13a. Therefore, the first region 12 and the third region 14 are used to eliminate the sub-grain boundary caused by the fourth region 15 and the second region 13. The first region 12 is used to melt and crystallize the corresponding non-crystallization region corresponding to the third region 14. The fourth region 15 is used to melt and crystallize the corresponding non-crystallization region corresponding to the second region 13.
When the mask 10 moves along an S-path to scan amorphous silicon layer 16, the first slits 12a is perpendicular to the second slits 13a, causing the poly-silicon grain direction and the grain boundary direction formed on the crystallization of the odd-numbered rows of the amorphous silicon layer 16 to be respectively different with that on the crystallization of the even-numbered rows of the amorphous silicon layer 16, largely affecting the electricity of the thin film transistor completed in subsequent manufacturing process.
The above problem of the grain direction and the boundary direction being different can be resolved if the scan direction of the mask 10 is changed to be fixed. For example, the mask 10 of FIG. 2 scans every row of the amorphous silicon layer 16 along the direction 17a from left to right. However, a longer manufacturing time is required.